1. Field of the Invention
The present invention relates to an electric charge detecting apparatus which performs charge-voltage conversion in a charge-coupled device (referred to as a CCD hereinafter).
2. Description of the Prior Art
In a conventional CCD, a signal charge has been detected by a so-called floating diffusion method (depicted as an FD method hereinafter), thereby to generate an output.
More specifically, the potential change has been detected by means of a floating diffusion amplifier by injecting signal charges into a floating diffusion layer according to the floating diffusion method. The floating diffusion amplifier is generally denoted by FDA which is described in "Characterization of Surface Channel CCD" by Marvin H. White, IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 1, 1974, pp. 1-13.
FIGS. 11(a) and 11(b) illustrate the structure of a conventional charge transfer device. FIG. 11(a) is a block diagram of the whole CCD. Photons entering a photodiode PD90 are converted to electric charges and accumulated in PD90. A predetermined time later, the electric charges are read out by a VCCD91 (Vertical CCD) and input to an FDA93 (Floating Diffusion Amp.) through an HCCD92 (Horizontal CCD), and finally detected as a voltage. FIG. 11(b) is a sectional view along A--A' line of FIG. 11(a). HCCD92 in FIG. 11(a) is formed of a P well 81, an n layer 88, n.sup.+ regions FD83 and RD86, a p.sup.- region 89 and a p.sup.+ layer all laminated on an n-type substrate 80, and polysilicon electrodes on the laminate via a gate oxide film 82. FDA93 is constituted of an FD83 and a source follower amplifier SFA87. The electric charge .DELTA.Q is input from HCCD92 to FD83 through an output gate OG84. Supposing that the parasitic capacitance present between FD83 and SFA87 is represented by C.sub.T and the gain of SFA87 is G.sub.T, the potential change .DELTA.V is expressed by an expression (1) below: EQU .DELTA.V=G.sub.T .multidot.Q/C.sub.T ( 1)
A reset pulse synchronized with a .phi.H signal is input to an RG85. A constant voltage V.sub.RD is impressed to an RD86. The electric charge .DELTA.Q input to FD83 is discharged to RD86 in accordance with the reset pulse of RG85.
FIG. 12(a) is a plan view of a general MOS transistor, and cross sections thereof along the lines A--A' and B--B' are indicated respectively in FIGS. 12(b) and 12(c). Referring to FIG. 12(b), a field oxide film 206 is a thick film obtained by a local oxidation method of silicon (LOCOS), and generally 0.5-1.0 .mu.m (5000-10000.ANG.) thick. In the transistor of FIG. 12, after a gate 96, a source 94 and a drain 95 are formed, interlayer films of BPSG, NSG or the like (not shown) are laminated, and then contact holes 97, 98 are opened by etching. The source 94 is connected with the drain 95 by an aluminum wiring.
The P.sup.+ region of the field oxide film 206 undesirably spreads further than in the initial state, as shown in FIG. 12(b), due to the thermal oxidation. Thereby, a capacitance Cb exists between the polysilicon gate 96 and P.sup.+ region. A gate oxide film 208 is 500-700.ANG. thick, and the field oxide film 206 is 5000-10000.ANG. thick. When the transistor operates, a channel 200 is constructed and therefore, a capacitance C6 is present also between the gate 96 and the channel 200. There is an overlap capacitance C7 between the gate 96 and the channel 200 at the drain side, which will be re-defined as a capacitance Cd. A source capacitance Cs is the sum of an overlap capacitance C5 and the capacitance C6. FIG. 13 is a diagram explanatory of the parasitic capacitance. Although SFA87 is constructed in two stages, only the first stage is shown in the drawing for the convenience of description. The parasitic capacitance is constituted as follows: EQU C.sub.T =C1+C2+C3+C4+C.sub.Tr ( 2) EQU C.sub.Tr +Cd+Cs.multidot.(1-G1)+Cb (3) EQU C.sub.L +C.sub.Tr2 +C.sub.dL +C.sub.Js ( 4)
wherein C1 and C2 are capacitances between FD83 and OG84 and between FD83 and RG85, C3 is a capacitance between FD83 and the P well 81, C4 is a capacitance of the wiring from FD83 to the drive transistor Tr in the first stage, G1 is a gain of the source follower in the first stage, and C.sub.Tx is an input capacitance from the drive transistor. In other words, the expression (3) represents that the capacitance Cs is lowered by nearly one digit because of the gain G1 (G1, G2=approximately 0.8-0.95), whereby C.sub.Tr, C.sub.T are decreased. C.sub.JS is a capacitance between the diffusion region at the source side of the drive transistor Tr and the P well 81, C.sub.dL is a capacitance between a gate and a drain (working also as a source of the drive transistor Tr) of a load transistor Tr, and C.sub.L is a load capacitance necessary to be driven by the source follower.
In the above-described constitution, there still remain such problems yet to be solved as 1) the parasitic capacitance and 2) mixing of noises into output signals, which will be depicted hereinbelow;
1) Parasitic capacitance: PA1 2) Mixing of noises into output signals: PA1 1. A buffer electrode is provided at both ends or one end of a gate electrode; PA1 2. A gate electrode is formed only in the active region of the transistor; PA1 3. The actual area of the PN junction is reduced by forming a contact hole to connect polysilicon on a voltage converter means with a source follower; PA1 4. A plurality of P wells are provided under a wiring connecting the voltage converter means and the source follower, to be connected with a source of the drive transistor in the source follower, whereby the parasitic capacitance is reduced; and PA1 5. P.sup.+ region under a field oxide film on which an output signal line from the source follower is wired is separated from other P.sup.+ region or no P.sup.+ region is provided, whereby mixing of noises is effectively suppressed.
The sensitivity should be improved in order to prevent the decrease of the saturated charges when the pixels are turned considerably fine, and therefore C.sub.T in the expression (1) should be eliminated. Moreover, it is also important to eliminate the parasitic capacitance so as to improve the frequency characteristic. Therefore, the parasitic capacitance, particularly, the overlap capacitance at the drain side should be eliminated to improve the sensitivity and the frequency characteristic. Besides, the PN junction capacitance and the wiring capacitance are required to be reduced to improve the sensitivity.
FIG. 14 is a sectional view showing the vicinity of the source follower and FIG. 15 is an equivalent circuit diagram of CCD. Only the first stage of the circuit is indicated in FIG. 15 for brevity's sake.
The PN junction capacitance is proportional to a contact hole 119 which is approximately 1.21*1.2 .mu.m.sup.2 at minimum at present, from the viewpoint of the stability of the process. Although the CCD part and FDA are separated by a field oxide film, actually they are not insulated because they use the P well in common. As is understood from FIG. 14, in a general CCD, FDA and VCCD, HCCD share the P well. That is, driving signals from VCCD, HCCD are mixed into an output signal Vo of FDA. Referring to FIG. 15, when signals are added to .phi.Vi-.phi.V4, .phi.H1, .phi.H2, the signals are impressed to the P well 81 through C31-C36. The influences when the potential of the P well 81 is scattered by the P well resistance and C20-C30 appear through C37-C40 of FDA. The changing component acts as noises, with inviting the S/N deterioration in the succeeding stage or inferior operation of CDS.
The output signals are mixed also on a signal wiring. FIG. 16 is a sectional view of a signal wiring part and an equivalent circuit diagram thereof. Generally, a signal line is formed of aluminum and wired on a field oxide film 212, as illustrated in FIGS. 16(a) and 16(b). The AL layer is generally 1 .mu.m thick, and the distance from the AL wiring to a P.sup.+ layer below the field oxide film 212 is also about 1 .mu.m. The distance between signal lines is approximately 10-20 .mu.m depending on the design of the mask, and each signal line is approximately 10 .mu.m wide. Assuming that S is the area of the overlap portion, .di-elect cons. is the dielectric constant of the oxide film, and d is the thickness of the oxide film, a capacitance C is represented by an expression (5) as follows; EQU C=.di-elect cons..multidot.S/d (5)
Therefore, C51-C53 are almost negligible in comparison with C41-C44 in the equivalent circuit of FIG. 16(b). The driving signals of .phi.H1, .phi.H2, RG, .phi.V1-.phi.V4 (not shown) are transmitted to the P.sup.+ layer (including the P well) through C41, C42, C44. Thereafter, as the P well resistance and C51-C54 take part, the P well potential is scattered and the signals are mixed into the output signal Vo through C43. This phenomenon is impossible to be prevented in the conventional example using the field oxide film.